发明名称 TRANSMISSION CIRCUIT, RECEPTIOIN CIRCUIT, TRANSMISSION/ RECEPTION CIRCUIT AND ELECTROOPTICAL DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To prevent particularly signal delay and malfunction in a reception circuit side in a circuit transmitting/receiving a logic signal through a capacitor. SOLUTION: A source voltage of a buffer 410 transmitting the logic signal in a transmission circuit 400 is boosted to (V1'-GND) larger than the source voltage (V2-V3) of the buffer 610 inputting the logic signal in the reception circuit 600. Thus, since the amplitude of the logic signal in an input point B is enlarged from (V2+Vf) being a clipping level by protective diodes D1, D2 to (V3-Vf), malfunction as well as signal delay is prevented.</p>
申请公布号 JP2001075540(A) 申请公布日期 2001.03.23
申请号 JP19990253505 申请日期 1999.09.07
申请人 SEIKO EPSON CORP 发明人 YATABE SATOSHI
分类号 G02F1/133;G02F3/00;G09G3/20;G09G3/36;G09G5/00;H03K19/017;H03K19/0175;(IPC1-7):G09G3/36 主分类号 G02F1/133
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