| 摘要 |
PROBLEM TO BE SOLVED: To avoid generating large frequency variation in the output clock signal of a PLL(phase-locked loop), in spite of switching reference clock signal having different phases. SOLUTION: In a clock-supplying device 100, a phase difference between a reference clock signal CK0 selected by a first clock selection circuit 101 and a comparing clock signal CKb is obtained by a phase comparator 105, this phase difference is smoothed by a loop filter 106 to output controlled voltage to a VCO(voltage-controlled oscillator) 107, thereby the output clock signal CKa of a frequency corresponding to the controlled voltage is oscillated from the VCO 107, and this clock signal CKa is frequency-divided by a frequency divider 108 to output various kinds of clock signals CKm and a comparing clock signal CKb. Then, a second clock selection circuit 102 is switched, the divider 108 is preset by the a reference clock signal CK1 selected by this switching and after then, a switch control circuit 103 executes control for simultaneously switching the circuit 101 and the circuit 102. |
