VERTICAL MOS SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To miniaturize a whole chip while a high breakdown voltage characteristic is maintained by specifying channel length a horizontal direction and the threshold voltage of a vertical MNOS transistor with respect to the main surface of a semiconductor substrate to the junction part of a well diffusion layer from the junction part of source diffusion layer. SOLUTION: A vertical MOS transistor is constituted of an N+semiconductor substrate 9, a second P-type diffusion area 30 being a well diffusion layer and an N+source diffusion area 14 being a source diffusion layer. Channel length to a horizontal direction is 1.4 to 2.0μm and the threshold voltage of the vertical MOS transistor is 1 to 5 V with respect to the surface of the semiconductor substrate from the junction part of the source diffusion layer 14 and the junction part of the well diffusion layer 30. Thus, the pattern are of the vertical transistor can be reduced by shortening channel length. The whole chip of the vertical MOS semiconductor device can be set to about 90% of a conventional one while a high breakdown voltage characteristic is maintained as it is.