发明名称 ARBITRATION CIRCUIT AND RECORDING MEDIUM DEVICE HAVING THE SAME BUILT IN
摘要 PROBLEM TO BE SOLVED: To smooth the pipeline processing a processing whose priority is low by compensating an access request and to accomplish an arbitration control that is not inconvenient, especially to recording and reproduction in real time. SOLUTION: When a frequency division clock obtained by performing frequency division of a reproduction clock or a recording clock from a disk part is inputted while requesters 101 and 102 output an access request REQ1, the requesters 101 and 102 output interrupt requests REQ1' and REQ2'. An adjusting part 201 receives such interrupt requests and allows the access requests of the requesters 101 and 102.
申请公布号 JP2001075861(A) 申请公布日期 2001.03.23
申请号 JP19990245864 申请日期 1999.08.31
申请人 SANYO ELECTRIC CO LTD 发明人 FUMA MASATO;OKAMOTO SANEYUKI
分类号 G06F12/00;(IPC1-7):G06F12/00 主分类号 G06F12/00
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