| 摘要 |
PROBLEM TO BE SOLVED: To compensate a phase without unnecessarily increasing the delay time of a variable delay circuit by switching one variable delay circuit to another variable delay circuit when the phase of the output of one selected variable delay circuit is different by one cycle from the phases of the outputs of other variable delay circuits. SOLUTION: This circuit is equipped with a 1st variable delay circuit 1, a 2nd variable delay circuit 2, a 3rd variable delay circuit 3, a 1st phase comparator 5 which compares the phase of the phase feedback signal 103 of a reference signal 102, a 2nd phase comparator 6 which compares the phases of the outputs of a plurality of variable delay circuits, a switching circuit 7 which switches the outputs of the 1st to 3rd variable delay circuits 1 to 3, and a control circuit 4. When the phase of the output of one variable delay circuit selected as a path for a clock signal is different by one cycle from the phases of the outputs of other variable delay circuits, the former variable delay circuit is switched to another variable delay circuit. Thus, phase compensation exceeding the delay time variation range of the variable delay circuits is enabled. |
