| 发明名称 |
Microcomputer with interrupt packets |
| 摘要 |
<p>An integrated circuit device (11) has an address and data path (15) interconnecting a CPU (12) with modules (14) the modules having event logic (8) to generate an event request packet having a destination address and the CPU decoding the packet to selectively respond to the request of the packet depending on the priority of the event. <IMAGE></p> |
| 申请公布号 |
EP0953913(A1) |
申请公布日期 |
1999.11.03 |
| 申请号 |
EP19990303255 |
申请日期 |
1999.04.27 |
| 申请人 |
STMICROELECTRONICS LIMITED |
发明人 |
JONES, ANDREW MICHAEL;MAY, MICHAEL DAVID |
| 分类号 |
G06F13/24;(IPC1-7):G06F13/24 |
主分类号 |
G06F13/24 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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