Pipeline device for SDRAM, includes register which supply data to corresponding data path in response to control signal output by control signal generation circuit

摘要

Registers (22,32,42) are arranged corresponding to input connection of data paths (20,30,40). A control signal generator (60) outputs pipe line control signals (PCLK1-PCLK3) to respective registers. The control signal generation circuit generates a pipeline control signal by the delay of a different pipeline control signal. Based on the received control signal, registers output data to corresponding data path. The data paths are connected between input and output connections (10,50) in cascade form. The transmission time (T1-Tn) is smaller than or equal to period (P) of the reference clock signals. At least one of the transmission times deviates from one of the other transmission times. An Independent claim is also included for method for producing control signals of pipeline device.