发明名称 PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER
摘要 PROBLEM TO BE SOLVED: To provide a PLL frequency synthesizer, from which spurious is removed. SOLUTION: This synthesizer is provided with a PLL circuit 4 for phase- comparing a reference signal obtained by frequency-dividing the frequency of a signal outputted from a DDS(digital direct synthesizer) 2 via a band-pass filter 3 by a first frequency dividing ratio and a comparing signal of a comparing frequency frequency-divided by a second frequency dividing ratio. The second frequency dividing ratio is set, so that the frequency of a spurious is equal to or higher than the cutoff frequency of a loop filter 5 in the circuit 4.
申请公布号 JP2001077689(A) 申请公布日期 2001.03.23
申请号 JP19990251004 申请日期 1999.09.06
申请人 KENWOOD CORP 发明人 MIYAKOSHI KUNIYASU
分类号 H03B28/00;H03L7/183;H03L7/197;(IPC1-7):H03L7/197 主分类号 H03B28/00
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