发明名称 |
Formal verifying method for development in data processor involves executing verification algorithm using one limit of signal envelope, and limiting state-space search by using verification algorithm |
摘要 |
A tracing program is determined by using a verification algorithm. The result of the determination of the tracing program is indicated on a graphical user interface. One limit of a signal envelope is then changed. The execution of the verification algorithm is then performed by using one limit of the signal envelope, and a state-space search is limited by the use of the verification algorithm. Independent claims are also included for the following: (a) a device for formal verification of development in data processor; (b) and a computer program for formal verification of development in data processor.
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申请公布号 |
DE10038499(A1) |
申请公布日期 |
2001.03.22 |
申请号 |
DE20001038499 |
申请日期 |
2000.08.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORP., ARMONK |
发明人 |
ANDERSEN, FLEMMING;BAUMGARTNER, JASON RAYMOND;ROBERTS, STEVEN LEONARD |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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主权项 |
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地址 |
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