| 摘要 |
A phase-locked loop system (1) comprising a quartz oscillator (11) locks the switching network clock to a clock phase from a central clock generator and outputs a low-voltage clock signal (CLK2) and a low-voltage frame-clock signal (FMB2) for normal bit-rate switching network structures. An analogue, discreet sinusoidal oscillator (VCO 6) uses a phase-locked loop (PLL2) to convert the normal bit-rate clock signal (CLK2) into a high frequency clock signal. A low-voltage pseudo-ECL device (23) produces by division a clock signal (CLK92) suitable for high bit-rate switching networks, after stabilising using a reference clock (74). The low-voltage pseudo-ECL device also outputs an equal frequency frame clock signal (FMB92) which is phase decoupled from the input frame clock signal (FMB2) and which is at a predetermined phase to the output clock signal (CLK92).
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