发明名称 INTRA-CHIP COMMUNICATION DATA COMPRESSION TECHNIQUE
摘要 PROBLEM TO BE SOLVED: To parallel perform a collation operation in compression and expansion and to perform efficient communication based on data compression between modules in a processor. SOLUTION: Data is compressed in a data transfer mode by using a memory and computing element integrated type parallel processor architecture for compressing and expanding data. Transmitting data is compressed in a compression module 3 of a module A1 and is transferred to a module B2. An expansion module 4 of a module B2 expands received data. In such a case, 'instantaneously decodable' algorithm, that is, such algorithm as to start to expand just after a module B receives data is used as compression algorithm. Then, it is possible to overlap expansion time 8 and transfer time 7.
申请公布号 JP2000181679(A) 申请公布日期 2000.06.30
申请号 JP19980356516 申请日期 1998.12.15
申请人 KAMEYAMA MITSUTAKA 发明人 KAMEYAMA MITSUTAKA;HARIYAMA SHIYOURON
分类号 G06F7/00;G06F5/00;G06F15/78;H03M7/30 主分类号 G06F7/00
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