发明名称 Reception apparatus and method
摘要 <p>A phase of a sampling clock provided from clock generating circuit 107 is switched periodically and alternately with a phase difference of 180 degrees, and during a period of each phase, timing estimating circuit 105 estimates a symbol timing. High-accuracy timing estimating circuit 109 selects an estimated result with higher reliability among symbol timing estimated results obtained in respective periods, thereby enabling estimation of the symbol timing with time resolution twice a sampling period. It is possible to decrease an operation frequency in an A/D conversion circuit even in a system requiring timing synchronization accuracy with high accuracy. &lt;IMAGE&gt;</p>
申请公布号 EP1085690(A2) 申请公布日期 2001.03.21
申请号 EP20000120026 申请日期 2000.09.14
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 ABE, KATSUAKI;ORIHASHI, MASAYUKI;MSUYA, JOB CLEOPA;SAGAWA, MORIKAZU;YONEYAMA, MASAYOSHI
分类号 H04L7/00;H04L7/033;(IPC1-7):H04L7/02 主分类号 H04L7/00
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