Dual loop phase-locked loop

摘要

The present invention relates to a dual loop phase-locked loop (PLL) architecture suited to integration on a silicon monolithic integrated circuit. The dual loop phase-locked loop includes two PLLs 13a, 13b. The output signal from the first PLL 13a is fed to a mixer 24 arranged in the feedback loop of the second PLL after an initial frequency divider 20b. This reduces the power consumption of the device because the mixer 24 is operated at a lower frequency as a result of the frequency division in the initial frequency divider 20b. The second PLL 13b phase-locks the output of the mixer 24 to a comparison signal. The output signal from the first PLL 13a is fed to the mixer 24 through an intermediate frequency divider 24. The mixer may be implemented digitally as a D-type flip-flop. <IMAGE>