发明名称 |
HIGHLY SELECTIVE AND COMPLETE INTERCONNECT METAL LINE AND VIA/CONTACT HOLE FILLING BY ELECTROLESS PLATING |
摘要 |
<p>A novel method for the activation of semiconductor substrates for highly selective electroless copper plating in multilayer interconnect metallization lines and vias/contact holes has been developed. A copper-seeded polysilicon layer is provided over the substrate to facilitate growth of copper into the vias. Subsequent rinsing and chemical-mechanical polishing processes allow removal of overgrowth of copper and the polysilicon layer to achieve overall smooth topography of the copper surface and the insulating layer surface of the substrate.</p> |
申请公布号 |
SG79235(A1) |
申请公布日期 |
2001.03.20 |
申请号 |
SG19980001811 |
申请日期 |
1998.07.16 |
申请人 |
NATIONAL UNIVERSITY OF SINGAPORE |
发明人 |
SAM LI FONG YAU;NG HOU TEE |
分类号 |
H01L21/288;H01L21/768;(IPC1-7):H01L21/768;C23C18/40;C23C18/30;H01L23/50;H01L23/485;H01L21/445;C23C18/54 |
主分类号 |
H01L21/288 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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