| 摘要 |
A static random access memory (SRAM) system that includes a five-transistor SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The cell voltage control circuit supplies the SRAM cell with the VCC supply voltage if the SRAM cell is not being written (i.e., during a read mode or a standby mode). If the SRAM cell is being written, the cell voltage control circuit supplies the SRAM cell with a cell voltage that is less than the VCC supply voltage. The lower cell voltage weakens pull-down transistors in the SRAM cell, thereby enabling logic high values to be written to the SRAM cell. In one embodiment, the cell voltage is less than the VCC supply voltage minus the threshold voltage of an access transistor of the SRAM cell. The cell voltage is high enough to enable the SRAM cell to reliably store data during a write disturb condition. A method of operating the five-transistor SRAM cell includes the steps of (1) powering the SRAM cell with a VCC supply voltage during a read mode, (2) powering the SRAM cell with the VCC supply voltage during a standby mode, and (3) powering the SRAM cell with a cell voltage less than the VCC supply voltage during a write mode.
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