| 摘要 |
A predriver circuit (25) includes a turn on drive circuit (251) having a first amplifier stage (M42, M39) receiving a first analog current and coupled to a second amplifier stage (M33, M1) defining a circuit output (201). The turn on drive circuit (251) is responsive to a first state of a digital clock signal (VCLK) to disable operation of a turn off drive circuit (252) and supply an amplified representation of the first analog current to the circuit output (201) with controlled slew rate for optimum switching speed and electromagnetic interference (EMI) performance. The predriver circuit (25) further includes a turn off drive circuit (252) having three amplifier stages (M26-27, M24-25, M14, M2-3) responsive to a second opposite state of the digital clock signal (VCLK) to disable operation of the turn on drive circuit (251) and draw an amplified representation of a second analog current from the circuit output (201) with controlled slew rate for optimum switching speed and EMI performance. The turn on and turn off circuits (251, 252) also include circuitry (M34, M36, I3, I4, N1-N4, M40, N5, I1, DM3, D1-D3, R9-10; DM5, M18, M23, I5-6, N10-13, M43, N8-9, DM4, M22, M19, M4-5) for minimizing power dissipation during respective operation thereof. The predriver circuit (25) of the present invention thus provides for high speed operation with optimum EMI performance in a high voltage environment while also minimizing power dissipation.
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