CAS latency control circuit

摘要

A Column Address Strobe (CAS) latency control circuit for a SDRAM and a layout of the same allows an adequate CAS latency operation allowance at a high operation frequency. The SDRAM includes a plurality of banks each having "n' main amplification units, "n' bit data buses disposed between the plurality of banks each shared by respective main amplification units, "n' CAS latency control circuits disposed concentrated central to the data buses one to one matched to the data buses, "n' DQ blocks disposed connected to outputs of respective CAS latency control circuits in lengths different from one another, and a clock buffer for applying a clock signal to the CAS latency control circuits.