| 摘要 |
In a semiconductor integrated circuit, a select signal output circuit switches a selector to take in the output of a circuit section in response to a signal "0" received at the D terminal thereof during normal operation. Thus, a scan flip-flop receives the output of the circuit section. During a scan test mode, a select signal "0" or "1" is input through a scan-in terminal to the select signal output circuit and then to the selector. If the select signal is "0", then the selector selects the output of the circuit section. On the other hand, if the select signal is "1", then the selector selects a clock signal supplied from a clock signal generator. The output of the circuit section or the clock signal supplied from the clock signal generator, which has been input to the scan flip-flop, is passed through a scan path and output to the outside through a scan-out terminal. As a result, an internally formed clock signal generator or the like can be tested easily.
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