发明名称 |
System and method for bit loading with optimal margin assignment |
摘要 |
A system and method which establishes an optimum margin for each channel in a discrete multi-tone (DMT) transceiver. The present system entails a discrete multi-tone transceiver which comprises a processor and a memory. Stored on the memory is operating logic which directs the function of the processor. The operating logic includes bit allocation logic and signal-to-noise (SNR) variation logic. The SNR variation logic determines an variation in the signal-to-noise ratio for each channel. The bit loading logic then determines a bit loading configuration based upon the variation in the signal-to-noise ratio ascertained by the SNR variation logic. The SNR variation logic preferably includes logic to determine the variation in the signal-to-noise ratio by means of statistical analysis, however, other approaches to determining the variation in the signal-to-noise ratio may be employed.
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申请公布号 |
US6205410(B1) |
申请公布日期 |
2001.03.20 |
申请号 |
US19980170749 |
申请日期 |
1998.10.13 |
申请人 |
GLOBESPAN SEMICONDUCTOR, INC. |
发明人 |
CAI LUJING |
分类号 |
H04L27/26;(IPC1-7):H04B1/40 |
主分类号 |
H04L27/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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