发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To realize high accuracy and low power consumption by slectrically isolating an element formation region for forming a clock generating circuit and an element formation region for constituting a digital circuit, which is formed on a semiconductor substrate. SOLUTION: Sence amplifier 2 are formed in respective memory cell arrays 1 of a memory chip where these amplifiers 2 are provided such that they are made to exist in the interior of respective triple wells forming the memory cell arrays 1. A DLL (clock generating circuit) analog part 3 is provided in the interior of a triple well in the central part of the memory chip, a triple well in the analog part 3 is provided so that it is made to be isolated from the triple wells including the arrays and the amplifiers 2 to make them adjacent to the part 3, and DLL digital parts 4 are made to exist on the outside of the triple wells. As a result, a low power consumption in a semiconductor integrated circuit device can be achieved with high accuracy. |
申请公布号 |
JP2001068650(A) |
申请公布日期 |
2001.03.16 |
申请号 |
JP19990243154 |
申请日期 |
1999.08.30 |
申请人 |
HITACHI LTD |
发明人 |
OKUDA YUICHI;KOKUBO MASARU;NAKAGOME YOSHINOBU;YAHATA HIDEJI;MIYASHITA HIROMOTO |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C11/401;G11C11/4074;G11C11/4076;H01L21/76;H01L21/822;H01L21/8242;H01L27/04;H01L27/10;H01L27/108;H03K5/13;H03K5/131;H03L7/00;H03L7/081;H03L7/089;H03L7/107 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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