发明名称 SYSTEM AND CIRCUIT FOR GENERATING DUPLICATION SIGNAL
摘要 PROBLEM TO BE SOLVED: To realize duplication signal system and circuit which can reduce a circuit scale and a system switch execution time to a system switch signal. SOLUTION: A method that separates a 0 system from a 1 system and adds ACT/SBY information to the respective systems is not used, but an ACT system is separated from a SBY system and subsequently, the signal is allocated to the 0 system and the 1 system. The number of ACT addition circuits or SBY addition circuits can be reduced by separating a system for the ACT system from a system for the SBY system. As to the ACT/SBY exchange of each system, communication is taken just before transmitting the signals of the ACT system and the SBY system after performing ACT and SBY signal addition.
申请公布号 JP2001069242(A) 申请公布日期 2001.03.16
申请号 JP19990244547 申请日期 1999.08.31
申请人 FUJITSU I-NETWORK SYSTEMS LTD 发明人 SHIMIZU ATSUKO
分类号 H04M3/22;H04L12/28;H04L12/60;H04L29/14;H04M3/00;H04Q3/545;H04Q3/56;(IPC1-7):H04M3/22 主分类号 H04M3/22
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