| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a non-volatile semiconductor memory capable of excluding a riskiness of an electrical breakdown and simultaneously obtaining a hierarchical bit line structure without increasing processing steps. SOLUTION: The non-volatile semiconductor memory comprises a plurality of matrixes of memory cells each having a floating gate and disposed on a silicon substrate, bit lines constituted of at least two-hierarchy main bit line 1 and sub-bit line 2, and a sub-bit line selecting transistor 4 provided between the main bit line 1 and the sub-bit line 2. In this case, a gate potential of the transistor 4 on a selected row address is set to the same as the gate potential of the transistor on a non-selecting row address in any of erasing and writing modes.</p> |
