| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL control circuit that reduces a frequency converging time due to a frequency jump in the case of switching an output frequency of a PLL circuit and to provide its control method. SOLUTION: A frequency division number of variable frequency dividers 104, 105 in the PLL circuit where the variable frequency dividers 104, 105 frequency-divide outputs of a reference oscillator 101 and a VCO 102 respectively and a phase comparator 106 compares the phase of them, is simultaneously switched by outputs of registers 108, 109 and an output of an S/P conversion circuit 110. Furthermore, serial data stored registers 114-116 are fed to the S/P conversion circuit 110 via a P/S conversion circuit 111 in a prescribed timing of a timer circuit 112.
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