发明名称 DC CLAMP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a DC clamp circuit where the input conversion range of DC fluctuation, which is contained in an analog signal, is not narrowed even if the amplification rate of an analog signal is changed and the follow-up ability of a DC clamp is not changed at the time of A/D-converting an analog signal containing DC. SOLUTION: The circuit has an adder 1, a first amplification circuit 2, an A/D converter 3, a comparator 4, a D/A converter 5, a switch 6, an integrator 7 and a second amplification circuit 8. The first amplification circuit 2 and the second amplification circuit 8 can independently set an amplification rate by gain control values CONT 1 and CONT 2. At the time of setting the amplification rate of the first amplification circuit 2, the amplification rate of the second amplification circuit 8 can be set by depending on the amplification set rate.
申请公布号 JP2001069372(A) 申请公布日期 2001.03.16
申请号 JP19990243524 申请日期 1999.08.30
申请人 ASAHI KASEI MICROSYSTEMS KK 发明人 TAKEUCHI SEIJI
分类号 H04N5/18;(IPC1-7):H04N5/18 主分类号 H04N5/18
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