SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To enhance a relief efficiency while reducing a circuit scale by setting a common element for storing defective addresses to address comparison circuits of a plurality of memory blocks having redundant circuits respectively. SOLUTION: In a memory of a prefetch system applied to a bit line redundant circuit, each of a memory array Me for even number addresses and a memory array Mo for odd number addresses has a normal column-selecting line and a redundant column-selecting line. Address comparison circuits YACe and YACo set corresponding to the memory arrays Me and Mo respectively share a fuse set YF. Defective addresses generated to normal circuits set to the memory arrays Me and Mo are registered into the fuse set YF. An address signal is inputted to the address comparison circuits YACe and YACo and compared with a defective address signal registered in the fuse set YF. When the signals agree, redundant select lines RYSe and RYSo are selected.