发明名称 REFERENCE POTENTIAL GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME
摘要 PROBLEM TO BE SOLVED: To correct a temperature dependency by outputting a promote signal when a delay time of a second delay circuit becomes larger than a delay time of a first delay circuit, outputting a restrict signal when the delay time of the second delay circuit becomes smaller than the delay time of the first delay circuit on the basis of output signals of the first and second delay circuits, raising a potential of an output line every time the promote signal is received, and reducing the potential every time the restrict signal is received. SOLUTION: A delay time at a second delay circuit 93 increases when a temperature rises, thereby increasing a difference of delay times between two delay circuits 92 and 93. The difference is detected by a delay time difference- detecting circuit 94 which in turn sends a promote signal to a programmable constant voltage-generating circuit 82 so as to raise a potential Vint of an output line 44. When the delay time at the second delay circuit 93 decreases to be smaller than a delay time at a first delay circuit 92, a restrict signal is sent to the programmable constant voltage-generating circuit 82, thereby lowering the stabilized voltage Vint on the output line 44. The stabilized output voltage Vint on the output line 44 is thus adjusted.
申请公布号 JP2001067873(A) 申请公布日期 2001.03.16
申请号 JP20000205962 申请日期 2000.07.07
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IWANARI SHUNICHI;SHIBAYAMA AKINORI;YAMADA TOSHIRO;FUJIWARA ATSUSHI
分类号 G11C11/407;H03K19/0944;(IPC1-7):G11C11/407;H03K19/094 主分类号 G11C11/407
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