| 摘要 |
PROBLEM TO BE SOLVED: To obtain an interruption controller capable of using a common CPU regardless of the necessity or unnecessity of multiple interruption and reducing the circuit scale of a CPU by reducing the function of the CPU to the irreducible minimum, and to obtain a microcomputer using the interruption controller. SOLUTION: In this microcomputer capable of multiple interruption, an interruption mask level register 46 which is provided at a CPU 2 side heretofore is provided at an interruption controller 4 side so that the CPU 2 can be miniaturized. The interruption controller 4 is constituted so that an interruption mask level in the interruption mask level register 46 can be saved to an RAM 6 according to a stack signal STK outputted by the CPU 2 simultaneously when the PSR (system register) value and PC(program counter) value of the interruption processing executed until that time are saved to RAM 6 at the time of starting interruption processing, and that the interruption mask level saved to the RAM 6 can be returned to the interruption mask level register 46 according to a return signal RTN outputted by the CPU 2 simultaneously when the PSR value and PC value are read from the RAM 6 at the time of resuming the interrupted interruption processing.
|
