发明名称 MATRIX ARRAY SUBSTRATE AND ITS MANUFACTURE
摘要 <p>PROBLEM TO BE SOLVED: To prevent a short circuit between a signal line and a scan line in a matrix array substrate for a planar display device including the signal lines each having a redundant line structure comprising an upper layer line and a lower layer line. SOLUTION: In an intersection part 7 of a signal line 6 and a scan line 11 in this matrix array substrate, a signal line lower layer line 51 is set to be sufficiently broad to absorb unevenness in an outline position of a signal line upper layer line 31. Accordingly, the signal line upper layer line 51 does not protrude out of a range of the signal line lower layer line 31 in the intersection part 7 so as not to cause a short circuit between the signal line upper layer line 51 and the scan line 11 even if a pinhole occurs at a position along the signal line 6 in an insulation film covering the scan line 11.</p>
申请公布号 JP2001067020(A) 申请公布日期 2001.03.16
申请号 JP19990245509 申请日期 1999.08.31
申请人 DISPLAY TECHNOLOGIES INC 发明人 SHIGENO HIROTAKA
分类号 G09F9/30;G02F1/136;G02F1/1368;H01L29/786;(IPC1-7):G09F9/30 主分类号 G09F9/30
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