| 摘要 |
PURPOSE: An integrated circuit memory having divided-well architecture are provided to restrain bit line external disturbances, without complicating a memory array and increasing the area. CONSTITUTION: An integrated circuit comprising memory cells arranged in rows accessed by word lines and columns accessed by bit lines, a first group of said memory cells formed in a first semiconductor region, and a second group of memory cells formed in a second semiconductor region that is electrically isolated from said first semiconductor region, wherein said bit lines run between said first group and said second group, and wherein a selected one of said first and second semiconductor regions is biased by a given voltage when a cell in a group formed in said selected region is accessed for a write operation, and biased at a voltage different than said given voltage when no cell in said selected region is accessed for a write operation, and a multiplexer that selectively connects a source of said given voltage to a selected one of said first and said second semiconductor regions.
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