A detector circuit (40) for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector (34) and compares the absolute magnitude of the error signal to a first threshold signal (limit 1) corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter (30) which continues counting so long as the error signal remains below the magnitude threshold value (limit 2). The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.
