| 摘要 |
The invention relates to a device for reliably erasing a volatile memory cell. A RAM cell substantially consists of two n or p channel transistors, whereby the gate terminal of one transistor is back-coupled to the output of the second transistor and the gate terminal of the second transistor is back-coupled to the output of the first transistor. The source connections of the transistors are grounded. The drain connections are connected to the power supply via resistors. According to the invention, at least one switch element is provided which is switched into an active position, once the RAM cell is disconnected from the power supply and which short-circuits the outputs of the RAM cell transistors. The electrically conductive connection between the complementary transistor outputs which are preferably grounded, generates an advantageous potential compensation which allows all the remaining charge carriers to drain, so that the previous memory content can no longer be determined.
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