发明名称 TEST METHOD FOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To easily conduct a single-body test of an integrated circuit connected to a peripheral circuit such as an LSI. SOLUTION: A mode selection control circuit C is provided between a core logic CL of an LSI 100 to be tested and its external connection terminal. In test mode, a previously set fixed value is outputted to the core logic instead of data inputted to the LSI 100 to be tested, and the output signal from the core logic CL is outputted to a peripheral circuit at a connection destination instead of the previously set fixed value. When a value making it possible to maintain the state before the peripheral circuit and LSI 100 to be tested send and receive signals after the printed board is powered ON is set as the fixed value, the peripheral circuit and LSI 100 are disconnected in test mode. In this state, a scan input signal is inputted and a test is conducted by a scan test method by using a scan flip-flop of the mode selection control circuit C and a scan flip-flop FF provided in the core logic CL.
申请公布号 JP2001066350(A) 申请公布日期 2001.03.16
申请号 JP19990242008 申请日期 1999.08.27
申请人 FUJI ELECTRIC CO LTD 发明人 AKAHA MASASHI
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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