DESIGNING CONDITIONAL SELECTIVE ADDER

摘要

PURPOSE: A conditional selective adder is provided to enhance an operation speed, reduce a current consumption by a level restore and a time delay block by selectiveing a pre-calculated sum based on a carry bit. CONSTITUTION: The unit comprises eight 8 bit conditional selective addition modules(10-80). Each 8 bit conditional selective addition modules(10-80) includes a PGB(Pre carry & sum Generation Block), a SGB(Sum Generation Block), and a CGB(Carry Generation Block). The carries generated from each 8 bit conditional selective addition modules(10-80) are all input into a BCGB(Block Carry Generation Block). The PGB(12) analyzes input values to be added at a first conditional selective addition module(10), and outputs a proper value in advance. At this time, the SGB(14) generates a sum in the case that a carry exists, and a sum in the case that a carry does not exist. The CGB(16) transmits the carry of the first conditional selective addition module(10) to the BCGB(90). At this time, the PGBs included in the remaining conditional selective addition modules(20-80) analyzes the input values to be added at the remaining conditional selective addition modules(20-80), and each SGBs generates a sum in the case that a carry exists, and a sum in the case that a carry does not exist.