摘要 |
Synchronization arrangement for clock generators and slave devices connected to a field bus, as used for example in industrial systems and communications receivers, require filtering of the jitter of the synchronization circuit by PLL circuits to give highly precise level of synchronization. Each slave device (3-7) is provided with a phase-lock-loop (PLL) circuit (10) which receives the synchronization signals on one side, and is loaded on the other side with the output pulses (T) of the clock generator of the respective slave device (3-7).
|