发明名称 Arrangement for synchronizing clock generator of several slave devices connected to field bus e.g. for industrial systems in communication devices
摘要 Synchronization arrangement for clock generators and slave devices connected to a field bus, as used for example in industrial systems and communications receivers, require filtering of the jitter of the synchronization circuit by PLL circuits to give highly precise level of synchronization. Each slave device (3-7) is provided with a phase-lock-loop (PLL) circuit (10) which receives the synchronization signals on one side, and is loaded on the other side with the output pulses (T) of the clock generator of the respective slave device (3-7).
申请公布号 DE19943724(A1) 申请公布日期 2001.03.15
申请号 DE19991043724 申请日期 1999.09.04
申请人 IMC MESSYSTEME GMBH 发明人 HILLENBRAND, FRANZ
分类号 G06F1/10;H03L7/06;(IPC1-7):H04L7/033;G06F1/12;G06F13/42 主分类号 G06F1/10
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