| 摘要 |
PURPOSE: An encoder of a multiplier is provided to enable each encoder cell and partial cell to output partial data, from a result of the multiplier of a multiplier number by a multiplicand number, within a 4 stage gate delay time so that it can enhance a speed of the multiplier and reduce component numbers. CONSTITUTION: The multiplier comprises an encoding unit and a partial product generation unit. The encoding unit, including a plurality of encoders, outputs a plurality of operators(0X, X, 2X, S) encoding multiplier data(Y0, Y1,..., Yn-1, Yn). The partial product generation unit, including a plurality of partial cells, outputs partial data(PPk1, PPk2, ..., PPkn-1, PPkn) in response to the operators(0X, X, 2X, S) and multiplicand data(X0, X1,.., Xn-1, Xn). The encoder includes exclusive NOR gates and NAND gates outputting combination signals, and inverters inverting the combination signals.
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