SWITCH DEVICE OF LINKED-LIST COMMON MEMORY

摘要

PURPOSE: A switch device of a linked-list common memory is provided to implement the control and management of a linked-list address only with pure hardware in an ATM switching using a common memory, and to consider hardware configuration to minimize the size of the memory and maximize a memory use rate. CONSTITUTION: A header detector(20) extracts a routing header tag during predetermined clocks, for outputting. A routing controller(30) outputs a write request signal. A cell data memory(40) reads cell data to output the cell data to an idle cell controller(90). A linked-list address memory(50) writes read addresses. A write/read address controller(60) requests the supply of write addresses to a free space cell data memory address FIFO(80), and outputs a read address of a next order to the linked-list address memory(50). If cell data corresponding to an output port are stored, the write/read address controller(60) outputs read addresses to the cell data memory(40) and the linked-list address memory(50). If signals for detecting an error and confirming whether to restore the error are inputted from an error detector(110), the write/read address controller(60) performs initialization of decision. The initial address manager(70) resets a counter used in generation of write addresses. The idle cell controller(90) generates and outputs idle cells The error detector(110) requests an output of idle cells to the idle cell controller(90). The read port controller(120) outputs an output port number to the write/read address controller(60), and receives the priority information from external.