| 摘要 |
PURPOSE: A method for fabricating a MOS transistor having an improved lightly doped drain(LDD) structure is provided. CONSTITUTION: A lightly doped n-type region(120A,120B) and a heavily doped n-type region(126A,126B) are sequentially formed in a p-type semiconductor substrate(112). The first insulating layer(130A,130B) is then formed thereon and patterned to define a gate region. Thereafter, a trench is formed in the substrate(112) by an isotropic etching process using the patterned insulating layer(130A,130B) as a mask. A spacer(145) of the second insulating layer is then formed on a sidewall of the trench, and a gate oxide layer(144) is formed on a bottom of the trench. Next, a conductive layer is formed on the entire surfaces and polished to expose the first insulating layer(130A,130B) and thus to form a gate layer(148a) in the trench. Since there is no overlap between the lightly doped n-type region(120A,120B) and the gate layer(148a), a capacitance reducing a switching speed is not produced. Furthermore, the generation of a hot carrier is controlled.
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