| 摘要 |
PURPOSE: An address signal generation part of a semiconductor memory is provided to suppress a delay during generating an address signal by using an address signal generation enable signal XAEBI faster than an address enable signal XAEI before the logic value of BXT and BXB are confirmed, and enabling address signals of BXT and BXB. CONSTITUTION: The address signal generation is occurred in NOR gates(408,412) and inverters(410,414). An external address BXIN becomes address signal BXT and BXB. The external address signal BXIN is inputted to an inverter(402) first and then is latched. A latch comprises two inverters(404,406). The output of the inverter(402) is inputted to the NOR gate(412), and the output of the inverter(404) is inputted to another NOR gate(408). The inverters(402,406) are tri-state inverters and are enabled by an address enable signal(XAEI) and its inverted signal. The inverter(402) is enabled when the address enable signal XAEI is in a low level. The inverter(406) of the latch is enabled when XAEI is in a high level, and latches an external address(BXIN) inputted through the inverter(402). That is, the input and the latch of the external address(BXIN) are accomplished during one period of the address enable signal(XAEI).
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