BRANCH INSTRUCTION FOR MULTITHREADED PROCESSOR

摘要

A parallel hardware-based multithreaded processor (12) is described. The processor (12) includes a general purpose processor that coordinates system functions and a plurality of microengines (22a-22f) that support multiple hardware threads or contexts. The processor (12) also includes a memory control system (16) that has a first memory controller (26a) that sorts memo ry references based on whether the memory references are directed to an even ba nk or an odd bank of memory and a second memory controller (26b) that optimizes memory references based upon whether the memory references are read referenc es or write references. Instructions for switching and branching based on executing contexts are also disclosed.