| 摘要 |
PURPOSE: To improve noise resistance of a semiconductor integrated circuit device and in addition, to reduce the cell area of the device by respectively arranging first conductor layers in regions surrounded by work lines and bit lines, with the center of the conductor layers which are deviated from the center line of an active region formed along a third direction. CONSTITUTION: With respect to the direction of word lines, the distance between the centers of adjacent upper capacitor electrode plugs 22 is made longer than that between the centers of adjacent lower capacitor electrode plugs 16. With respect to the direction of bit lines, in addition, the distance between the centers of the adjacent upper capacitor electrode plugs 22 is made shorter than that between the centers of the adjacent lower capacitor electrode plugs 16. Consequently, short-circuiting with the bit line can be prevented, without using the self-aligning contact forming technique. Since the lower capacitor electrode plugs 16 are opened to be large, in addition, sufficient plug superposition can be secured even if the upper capacitor electrode plugs 22 are offset.
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