| 摘要 |
PURPOSE: A method for fabricating a capacitor having a metal insulator metal structure in a merged DRAM and logic device is provided to improve a step coverage property of a dielectric layer and to prevent a concentration of an electric field on a specific portion of the dielectric layer. CONSTITUTION: After the first insulating layer(102) is formed on a semiconductor substrate(100), the first conductive layer(104) is formed thereon. A capping metal layer(106) having a titanium layer(106a) and a titanium nitride or titanium tungsten layer(106b) is formed on the first conductive layer(104) and then selectively etched together with the first conductive layer(104) to form a lower electrode(I). The second insulating layer(108) is formed thereon and then selectively etched together with the capping metal layer(106) to form a via hole. Here, the capping layer(106) has a sloped-sidewall in the via hole. Thereafter, a dielectric layer(110) and a barrier metal(112) are sequentially formed in the contact hole and on the second insulating layer(108), and a plug(114) is formed in the via hole. Next, the second conductive layer(116) is formed to form an upper electrode(II) together with the plug(114).
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