| 摘要 |
PURPOSE: A semiconductor memory device and a method for controlling a memory cell array block thereof are provided to prevent the increase of input/output lines, and thus to prevent the increase of the area of the memory cell array block even if a bandwidth is increased. CONSTITUTION: In case that a bandwidth is 4 bit, one of sub array blocks is selected by one row address applied from the external. That is, one word line(1WL1) of a sub array block(41)is selected and activated. And, 4 bit line pairs(1BL0/1BL0B-1BL3/1BL3B) of 4 memory cells connected to the word line(1WL1) are connected to 4 input/output line pairs(IO0/IO0B-IO3/IO3B). Thus, the first 4 bit data is written to or read from 4 memory cells via four input/output line pairs arranged right and left of a sub array block(41). And, another sub array block is selected by another row address applied from the external, and one word line(3WL1) of a sub array block is activated. And, the second 4 bit data is written to or read from four memory cells via four input/output line pairs(IO4/IO4B-IO7/IO7B). In case that the bandwidth is 8 bit, two sub array blocks(41) among sub array blocks(211-21n). That is, one word line(1WL1) and of the sub array block(41) and one word line(3WL1) of the sub array block are selected and activated at the same time by one row address. And, four bit line pairs(1BL0/1BL0B-1BL3/1BL3B) of four memory cells connected to the word line(1WL1) are connected to four input/output line pairs(IO0/IO0B-IO3/IO3B) by activating column selection lines corresponding to column addresses applied from the external, and four bit line pairs(3BL0/3BL0B-3BL3/3BL3B) of four memory cells connected to the word line(3WL1) are connected to four input/output line pairs(IO4/IO4B-IO7/IO7B). Therefore, 8 bit data are written to or read from 8 memory cells via eight input/output line pairs(IO0/IO0B-IO7/IO7B). Also, in case that the bandwidth is 16 bit, four sub array blocks are selected by one row address applied from the external, and data is written to or read from 16 memory cells according to the above procedure.
|
