发明名称 Method of designing semiconductor integrated circuit and apparatus for designing the same
摘要 A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the semiconductor integrated circuit, estimates a voltage drop value due to the calculated leak current, determines whether or not the voltage drop value exceeds a threshold value for each node, and inserts a buffer to a node determined that the voltage drop value exceeds the threshold value.
申请公布号 US2006225013(A1) 申请公布日期 2006.10.05
申请号 US20050316744 申请日期 2005.12.27
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ITAKA YASUHITO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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