发明名称 Using epitaxially grown wells for reducing junction capacitances
摘要 The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.
申请公布号 US6200879(B1) 申请公布日期 2001.03.13
申请号 US19980210271 申请日期 1998.12.10
申请人 INTEL CORPORATION 发明人 TYAGI SUNIT
分类号 H01L21/762;H01L21/8238;(IPC1-7):H01L21/76 主分类号 H01L21/762
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