发明名称 |
Dynamic RAM, semiconductor storage device, and semiconductor integrated circuit device |
摘要 |
There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g., the circuit ground level indicating a non-selection level are supplied to a word line connected to the dynamic memory cell.
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申请公布号 |
US6201728(B1) |
申请公布日期 |
2001.03.13 |
申请号 |
US19990101009 |
申请日期 |
1999.02.08 |
申请人 |
HITACHI, LTD.;HITACHI ULSI ENGINEERING CORP. |
发明人 |
NARUI SEIJI;NAGASHIMA OSAMU;HASEGAWA MASATOSHI;FUJISAWA HIROKI;MIYATAKE SHINICHI;SUZUKI TSUYUKI;AOKI YASUNOBU;TAKAHASHI TSUTOM;KAJIGAYA KAZUHIKO |
分类号 |
G11C7/06;G11C11/4091;H01L27/108;(IPC1-7):G11C11/24 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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