| 摘要 |
For a system having multiple sources of digital input data to be converted to analog by Digital to Analog Converters (DACs), pre-processing of the multiple sources of data is provided, such that differences in input sampling rates are accommodated. When multiple digital input sources are to be converted to analog signals in a single integrated circuit, these input signals are routed to a clock generator having Phase Locked Loop (PLL) circuitry and to respective Asynchronous Sample Rate Converters (ASRCs). Sample rate information relating to an input signal selected from among the multiple input signals is determined during a locking operation of the PLL. Based on the common clock output from the clock generator, the ASRCs convert the input signals to a single sampling rate. Once the multiple input sources are converted to a common sample rate by the ASRCs, the inputs are converted to analog signals by DACs using the common clock and are output by the single Integrated Circuit.
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