Digitally switched potentiometer having improved linearity and settling time

摘要

A digitally switched potentiometer has improved linearity by minimizing the amount of resistive error introduced by switches used to switch the resistive elements comprising the potentiometer. Improved settling time of the potentiometer is achieved by reducing the amount of switch capacitance connected to the output of the potentiometer. The digitally switched potentiometer may be fabricated on an integrated circuit die and the switches may be fabricated with complementary metal oxide semiconductor (CMOS) transistors. The number of resistors needed for a desired number of resistive step changes is reduced by using two major resistor ranks and one minor resistor rank, or two minor resistor ranks and one major resistor rank connected in series.