发明名称 Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator
摘要 A pseudo-random built in self test pattern generator is constructed of eight sequential D-flip flops and configured to output 10-bit wide pattern data which conforms to the 8B/1OB transmission protocol. The first and fifth D-flip flops of the array have their outputs split, with one leg of the split directly defining a character bit and the other leg of the split defining an inverted character bit. The outputs of the first, second, seventh and eighth D-flip flops are directed to a four input EXOR gate whose output is connected to the D input of the first D-flip flop of the array. Configured as a recirculating feed back loop, the pattern generator defines a sequence of 10-bit patterns in which no more than five sequential 1s or five sequential 0s are generated either within a pattern or on pattern boundaries. The pattern generator provides 255 Fiber Channel-type transmission characters to a Fiber Channel-type transceiver circuit which serializes the characters into a 1.06 GHz serial datastream and then deserializes the datastream into 10-bit transmission characters. The received transmission characters are analyzed and if they match with patterns transmitted, the transceiver circuit is deemed to be correctly operating at a 1.06 GHz characteristic frequency.
申请公布号 US6201829(B1) 申请公布日期 2001.03.13
申请号 US19980055197 申请日期 1998.04.03
申请人 ADAPTEC, INC. 发明人 SCHNEIDER THOMAS R.
分类号 H04L1/24;(IPC1-7):H04B1/38;H04L5/16 主分类号 H04L1/24
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