| 摘要 |
A host adapter integrated circuit has a dedicated circuit which detects an attempted access of a digital resource (for example, SCSI bus interface circuitry) from a system bus (for example, a PCI bus) and automatically generates a pause request signal to stop instruction execution of a sequencer of the host adapter integrated circuit. The sequencer stops executing instructions, the sequencer is decoupled from the digital resource, and the digital resource is coupled to the system bus. With the digital resource coupled to the system bus, the system bus access of the digital resource is completed. In some embodiments, a pause acknowledge signal is generated by bus transfer logic of the sequencer to indicate that the digital resource can be accessed from the system bus. This pause acknowledge signal is used to generate a ready signal onto the system bus. The digital resource is therefore accessed from the system bus in one system bus cycle, an attempted access by a device on the system bus is not interrupted by another device on the system bus, and the accessing device need perform no special polling.
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