| 摘要 |
An MSK modulator which performs an accurate MSK modiation with high speed digital data is provided. When a to-be-modulated digital signal is provided from a code generator 1, a bidirectional shift register 2 allows a bit-row with sixteen bits to shift in circulation in a direction determined in accordance with a logic value of the supplied digital signal. Weighting adders 3I and 3Q weight and add logic values of the fifth to twelfth least significant bits in the bit row and logic values of the first to eighth least significant bits in the bit row. Two analog signals each of which is generated by the weighting adders 3I and 3Q are out of phase to each other by (pi/2) radians. The analog signal generated by the weighting adder 3I is multiplied by a signal generated by a first local oscillator 7, whereas the analog signal generated by the weighting adder 3Q is multiplied by a signal generated by a phase shifter 8. An adder 9 adds these multiplication results to generate an MSK modulation wave.
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